;fill-opacity:1'/%3e%3cpath%20fill='%230f0f0f'%20d='m14.354%2019.12.274-6.354-4.114.548-3.565%201.04.274%203.074%202.194%203.017%202.469-.274zm3.566-2.789%201.37%203.017h3.017l2.194-.274%201.097-3.84.275-3.291-4.663.274-3.565%201.04z'%20style='fill:%230f0f0f;fill:color(display-p3%20.0588%20.0588%20.0588);fill-opacity:1'/%3e%3cpath%20fill='%23f3ea37'%20d='M27.738%2011.36c-.209-.229-8.8-.877-9.746.454-.445.627-.806%201.543-1.612%201.65-.806.105-1.21-1.577-2.245-1.824-1.036-.246-9.783%202.033-10.03%202.595-.246.56-.019%201.894.26%202.068.276.177%201.318-.42%201.567-.233.246.188%202.295%204.564%202.734%204.933.44.37%205.4-.246%205.82-.84.42-.598%201.088-4.278%201.3-4.666.21-.386%201.087-.702%201.403-.14.316.56.84%204.166%201.42%204.532.578.367%205.645.464%206.363-.184.72-.649%201.628-5.775%201.837-6.056.212-.281%201.02-.292%201.144-.573.12-.279-.003-1.49-.215-1.717M13.843%2019.1c-.316.578-3.682%201.237-4.365.971-.683-.262-2.735-4.392-2.341-5.26s6.548-2.21%207.127-1.708c.581.5-.104%205.418-.42%205.996m10.454-.103c-.185.185-4.457.34-4.904-.029s-1.13-5.581-.659-5.972c.474-.392%206.444-.558%206.838%200%20.396.554-1.09%205.817-1.275%206.001'%20style='fill:%23f3ea37;fill:color(display-p3%20.9529%20.9176%20.2157);fill-opacity:1'/%3e%3c/svg%3e)
;fill-opacity:1'/%3e%3cpath%20fill='%23000'%20fill-rule='evenodd'%20d='M7.249%203.2c.469%200%20.85.38.85.85v3.893l1.873%201.874a.849.849%200%201%201-1.2%201.2L6.896%209.145A1.7%201.7%200%200%201%206.4%207.943V4.049c0-.469.38-.85.849-.85'%20clip-rule='evenodd'%20style='fill:%23000;fill-opacity:1'/%3e%3c/svg%3e)
;fill-opacity:1'/%3e%3c/svg%3e)
Lecture on superscalar techniques, memory data flow, VLIW, and EPIC processors from a Czech university course, including links to resources and recordings.
Lecture 05 – Superscalar Techniques and Memory Data Flow in Computer Architecture
Loading comments...
;fill-opacity:1'/%3e%3cpath%20fill='%23fff'%20d='M30.21%2019.84A15.2%2015.2%200%200%200%2038.334%2028H30.21zM58.095%2028H49.97a15.2%2015.2%200%200%200%208.125-8.16zM38.335%200a15.2%2015.2%200%200%200-8.126%208.158V0zm19.76%208.158A15.2%2015.2%200%200%200%2049.97%200h8.125z'%20style='fill:%23fff;fill-opacity:1'/%3e%3c/svg%3e){kind=small}
![Pavel Pisa: Advanced Computer Architectures - 08 (Memory Consistency) [2021/22]](https://static.tom3.com/lazy-static/thumbnails/18a6f44a-2d29-4dc3-aebc-83511dd4834e.jpg?preview=82240965-fe71-4b6a-b2d1-f21bf6b3d37f)
![Pavel Pisa: Advanced Computer Architectures - 10 (Parallelism II - OpenMP and MPI) [ZS 21/22]](https://static.tom3.com/lazy-static/thumbnails/dbb11b98-997e-4901-95d5-be937b2d432b.jpg?preview=e5c71615-12c0-4feb-8f5b-8ce589da4d11)
![Pavel Pisa: Advanced computer architectures - 02a (introduction to Verilog language) [ZS 21/22]](https://static.tom3.com/lazy-static/thumbnails/2a4ad3d9-f989-480b-b1e2-788ba3ea0868.jpg?preview=0af74d1c-7299-4a8d-aba4-20a474520978)
![Pavel Pisa: Advanced computer architectures - 13a (ARM and RISC-V architecture) [ZS 21/22]](https://static.tom3.com/lazy-static/thumbnails/31fa5e66-8263-48f5-9d64-da71bdfc6675.jpg?preview=f20f5fe0-0272-4a1e-821d-c1e0eb83cc65)
![Pavel Pisa: Advanced computer architectures - 04 (instruction pipeline inside CPU) [ZS 21/22]](https://static.tom3.com/lazy-static/thumbnails/560f70d0-dee6-4405-8072-eef86ea48b72.jpg?preview=44d73ec6-fd8d-48c1-88c8-7d72550d29a6)